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Chapter 2:
Functional Description
The TSMAC IP core is a fully synchronous machine composed of Transmit and Receive MAC sections that operate
independently to support full duplex operation.
The block diagram of the TSMAC IP core is shown in Figure 2-1 . The major functional modules are:
? Host Interface
? Receive MAC
? Transmit MAC
? Internal Buffers and FIFO Interfaces
? G/MII
? Management interface module (optional)
In the 1G mode, the 125 MHz system clock is supplied to the Transmit MAC. The system clock is used to clock the
GMII interface for data transmission. When receiving data, an external PHY device provides the 125 MHz clock to
the GMII receive section. The 125 MHz clock is used to clock the Receive MAC.
In the 10/100 mode, an external PHY device supplies the clock to the Transmit MAC and the Receive MAC.
Configuration Options
The TSMAC IP core supports three basic configuration options:
? Classic TSMAC with G/MII
? Gigabit MAC with GMII
? SGMII Easy Connect MAC with GMII.
Classic TSMAC Option
When the Classic TSMAC option is selected, the TSMAC IP core can be configured to operate in either the 1G
mode (1000Mbps data rate) or the Fast Ethernet mode (10/100 Mbps data rate). A block diagram of the Classic
TSMAC IP core option is shown in Figure 2-1 . Operation in either 1G mode or Fast Ethernet mode is selected by
setting an internal register bit.
IPUG51_03.0, December 2010
7
Tri-Speed Ethernet MAC User’s Guide
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